(1) Field of the Invention
The present invention relates to an apparatus and method for processing data in accordance with programs, and particularly to such an apparatus and method provided with a plurality of flag groups to be changed in accordance with calculation results of a plurality of data having different widths.
(2) Description of the Related Art
Recently, data processing apparatuses such as micro computers with 16-bit or 32-bit MPU (Micro Processing Unit) have been realized along with the improvement of data processing performance and demand for higher functions. These data processing apparatuses can calculate data having a plurality of different widths, such as 16 bits and 32 bits, and some of the apparatuses are provided with two or more flag groups depending on the purpose of calculations.
FIG. 1 is a block diagram showing the construction of a first conventional data processing apparatus with two flag groups, which is disclosed in Japanese Laid-open Patent Application No. 54-117646. The apparatus is provided with an instruction decoding unit 41 for decoding instructions, a calculator 42 for calculating 16-bit data, a first flag group 43 for conditional branch judgement, a second flag group 44 for arithmetic operations, and a branch judging unit 45 for judging whether a branch is taken or not.
When an instruction decoded by the instruction decoding unit 41 is an arithmetic operation instruction, the calculator 42 performs an arithmetic operation. The flags in the first flag group and the second flag group are changed in accordance with the results of the operation.
If the next instruction decoded by the instruction decoder unit 41 is an arithmetic operation instruction again, the calculator 42 performs another arithmetic operation by referring to the second flag group 44. The first and second flag groups 43 and 44 are changed in accordance with the results of the arithmetic operation.
On the other hand, if the next instruction is a conditional branch instruction, the branch judging unit 45 judges whether a branch is taken or not from the first flag group 43 for conditional branch.
However, according to the first conventional data processing apparatus, these flag groups 43 and 44 are both designed for 16-bit data. Therefore, data with fewer bits must be extended so as to fit the data width of the calculator 42.
FIGS. 2A and 2B show how 8-bit data is processed in the 16-bit calculator 42, as an example of data extension.
When two 8-bit data 88H and F8H are added (H represents hexadecimal), they are made into 16-bit data by filling zeros or ones in higher bits. In the case where a branch is performed based on 8-bit unsigned data shown in FIG. 2A, the higher 8 bits are filled with zeros. In the case the data is regarded as 8-bit signed data, the value 1 on the 8th bit is extended to the higher 8 bits shown in FIG. 2B. Thus, an additional process of extending data is inevitable, which leads to the increase in process overhead.
FIG. 3 is a block diagram showing the construction of a second conventional data processing apparatus with two flag groups, which is disclosed in Shokodo's "16-bit micro processor 8086 family", March, 1982.
The apparatus is provided with an instruction decoding unit 61 for decoding instructions, a 16-bit calculator 62 for calculating data, a flag group 63 to be changed based on the result of either an 8-bit operation or a 16-bit operation, a selector 64 for selecting each input of the flag group 63 which is changed based on either the 8-bit operation or the 16-bit operation, a flag group 65 to be changed based on the result of 4-bit operation, and a branch judging unit 66 for judging whether a branch is taken or not from the flag group 63.
FIG. 4A shows the bit configuration of a machine language instruction for ADD, SUBTRACT, and COMPARE instructions, and FIG. 4B shows the bit configuration of a machine language instruction for conditional branch instructions. In the bit configuration shown in FIG. 4A, a bit in the first byte (shown by W in operation) is assigned to indicate data width in addition to the arithmetic operation type. The second byte is assigned registers to be operated and addressing mode for memory operands, the third and fourth bytes are assigned for address in memory. In the bit configuration shown in FIG. 4B, four bits in the first byte (operation code) are assigned a branch condition.
The above-mentioned data processing apparatus operates as follows.
First, an instruction is decoded by the instruction decoding unit 61. When the instruction is an arithmetic operation instruction, the calculator 62 performs an arithmetic operation. The flags in the flag group 63 and 65 are changed, based on the results of the operation. At this time, the instruction decoding unit 61 designates data width (8 bits or 16 bits) to the calculator 62 and then the selector 64 outputs flag changing data determined by the data width a bit field to the flag group 63.
The next instruction is decoded by the instruction decoding unit 61. In the case where the instruction is a conditional branch instruction, the branch judging unit 66 judges whether the branch is taken or not from the flag group 63. In the case where an instruction which follows an arithmetic operation is an arithmetic operation for decimal data, the calculator 62 performs the operation by referring to the flag group 65.
According to the second conventional data processing apparatus, the use of the flag group 65 based on 4-bit operation, which is changed concurrently with the flag group 63 based on either 8-bit operation or 16-bit operation is limited to arithmetic operations for decimal data and cannot be applied to conditional branch.
Thus, the second conventional data processing apparatus has successfully overcome the problem of process overhead by selecting between the two flag changing data depending on the two data widths of 8-bit and 16 bit. However, data width is designated in an instruction, so that two instruction code assignments (one for 8-bit data and the other for 16-bit data) are needed for each arithmetic operation. This brings about a problem of complicating the construction of the instruction decoding unit because of enlargement of instruction code assignment.